Circuit for reading non-volatile memories

ABSTRACT

A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.

FIELD OF THE INVENTION

[0001] The present invention relates to memory devices, and inparticular, to a reading circuit of the voltage-sensing type for readingnon-volatile memory cells in a memory device.

BACKGROUND OF THE INVENTION

[0002] The storage of a data in digital form in a non-volatile memorycell such as, for example, a flash electrically erasable programmableread-only memory (EEPROM) cell takes place by suitable programming ofthe threshold voltage of the cell. The need to use memory devices withever higher capacities has made multilevel memories particularlyadvantageous. Theoretically, in a multilevel memory, the thresholdvoltage of a cell of the memory can be programmed not merely to one oftwo possible levels (as is the case for two-level cells) but to one of2^(n)−1 levels, enabling n bits to be stored in a single cell.

[0003] Two different techniques are known for reading the data stored ina memory cell. According to one of these techniques, known as currentsensing, the reading is performed while the voltages applied to thedrain, to the source, and to the gate of the memory cell to be read arekept constant and at a suitable value. In similar conditions of biasing,the cell addressed will therefore absorb a drain current which dependson its programming state.

[0004] In contrast, the other reading technique, which is known asvoltage sensing, provides for the reading to be performed while thedrain current absorbed by the cell addressed is kept constant and thebiasing conditions at the drain and source terminals are fixed. Inparticular, voltage sensing takes place by acting on the gate voltage toforce the memory cell to absorb a predetermined current. The thresholdvoltage programmed in the cell, which is unequivocally correlated withthe gate voltage, can be determined by evaluating the gate voltage whichbrings the cell to absorb this current in steady-state conditions, andthus deriving the data stored in the cell. In one of its possible forms,this reading technique requires a control circuit which regulates thegate voltage applied to the cell in order for the cell to absorb thepredetermined current.

[0005] U.S. Pat. No. 6,034,888 describes a voltage sensing readingcircuit in which a negative feedback circuit is used. The feedbackcircuit comprises an operational amplifier which receives the drainvoltage of the memory cell to be read at a non-inverting input, and abiasing voltage at an inverting input. This operational amplifieroutputs the voltage to be applied to the gate terminal of the cell. Thetimes required to reach a steady state, which are indicated in thepatent, may be 1 μs or 500 ns, according to the particular circuitconfiguration. Moreover, in this patent, it is pointed out that the node(indicated by the numeral 16) of the feedback circuit described withreference to FIG. 1, therein which connects the non-inverting input ofthe operational amplifier to the drain terminal of the memory cell, maycause instability in the reading circuit.

[0006] The instability of the reading circuit formed in accordance withthis patent is attributable to the presence of high-impedance nodes towhich low-frequency poles of the transfer function of the feedbackcircuit correspond. This instability represents a considerabledisadvantage, since it necessitates the use of additional compensationcircuits which, as well as making the circuit configuration complex,brings about an increase in the reading times. That is, there is anincrease in the time taken to reach the steady state in which the dataprogrammed in the cell is evaluated. Moreover, it is pointed out thatthe above mentioned patent does not address problems connected withpower consumption by the circuit.

[0007] In the construction of integrated devices in semiconductor chips,such as memories, there is a tendency to reduce the supply voltage bybringing it down, for example, to values of 3 V or 1.8 V. This tendencyconflicts with the need, which is characteristic of reading circuits inthe multilevel context, to supply the memory cell to be read with a gatevoltage greater than that of the supply in order to interact correctlywith the cell.

[0008] This need is thus pressing for multilevel cells, since a wideningof the range of voltages applicable to the gate terminal of the memorycell renders the discrimination of the threshold programmed among anumber of possible values, which is required to be as high as possible,less critical. In order to supply sufficiently high voltages,conventional reading circuits make use of integrated positivevoltage-booster devices.

[0009] It is pointed out that, in order to read memories with a largenumber of cells, the area in the semiconductor chip intended for thepositive voltage-boosters and the power absorbed thereby, may becomeconsiderable. It is therefore essential to provide reading circuits forwhich the dimensions and/or the number of positive voltage-boosters usedis limited.

SUMMARY OF THE INVENTION

[0010] In view of the foregoing background, an object of the presentinvention is to provide a reading circuit for reading memory cells whichdoes not have the disadvantages indicated above with reference toconventional reading circuits.

[0011] This and other objects, advantages and features are achieved by areading circuit for reading a non-volatile memory cell having an outputterminal for an output current, and a control terminal for receiving avoltage for controlling the output current. The reading circuitcomprises a feedback circuit which can be connected electrically to theoutput terminal and to the control terminal to generate the controlvoltage from a reference signal and from the output current.

[0012] The feedback circuit comprises current-amplification means havinga first terminal for receiving a current error signal derived from thereference signal and from the output current, and a second terminal forsupplying an amplified current.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The characteristics and advantages of the present invention willbecome clear from the detailed description of a preferred embodimentthereof, provided purely by way of a non-limiting example and given withthe aid of the appended drawings, in which:

[0014]FIG. 1 is a block diagram of a reading circuit for reading memorycells in a memory device according to the present invention; and

[0015]FIG. 2 is a more detailed schematic diagram of the reading circuitillustrated in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016]FIG. 1 shows, by functional blocks, a particular circuit forreading a matrix of memory cells 1. The reading circuit comprises acolumn decoder 4, a column voltage limiter or bitline limiter 8, afeedback circuit 100, an analog/digital converter 5, and a line decoder3.

[0017] The memory matrix 1 comprises a plurality of non-volatile memorycells of which a single memory cell 2 is shown in FIG. 1. The cell 2 is,for example, of the two-level or multilevel flash EEPROM type. As isknown, a cell of this type uses a floating gate metal oxidesemiconductor field-effect transistor (MOSFET) for which the storage ofdata takes place by suitable programming of the threshold voltageV_(th).

[0018] In greater detail, the memory cell 2 has a source terminal Sconnected to ground, a drain terminal D connected to the column decoder4, and a gate terminal G connected to the line decoder 3. The columndecoder 4 and the line decoder 3, which are formed for example, in aconventional manner, enable a column and a line, respectively, of thememory matrix 1 to be selected on the basis of a suitable address signalADD, so as to address a memory cell.

[0019] In the embodiment of FIG. 1, the column decoder 4 enables thedrain terminal D of the memory cell 2 to be connected, by the bitlinelimiter 8, to an input terminal 9 of the feedback circuit 100. The linedecoder 3 enables the gate terminal G to be connected, by a conductivebranch 16, to an output node or terminal 7 of the feedback circuit 100.The bitline limiter 8 enables the voltage of the drain terminal D of thememory cell 2 selected by the decoders 3 and 4 to be kept at a suitablevalue. This bitline limiter 8 may be formed in a conventional manner.

[0020] The circuit comprising the memory cell 2 and the reading circuitof FIG. 1 is a voltage sensing circuit with negative feedback. Thefeedback circuit 100 supplies to the gate terminal G of the memory cell2 a control or regulating voltage to force the cell to absorb a currentof predetermined value. The reading circuit of FIG. 1 and the memorymatrix 1 are preferably formed in a single integrated circuit on a chipof semiconductor material.

[0021] The feedback circuit 100 comprises a low-voltage stage 101 and ahigh-voltage stage 102. The low-voltage stage 101 includes a currentmirror 10 formed, for example, by P-type MOSFETs and has an input branchconnected to the input terminal 9 and an output branch connected to anode 11. The current mirror 10 enables a current mI which is a multiple,by a factor m, of the current I present at the input terminal 9, to besupplied to the node 11. The node 11 is also connected to a currentgenerator 12 which can generate a reference current I_(REF). The currentmirror 10 is supplied by a voltage V_(dd) such as, for example, thestandard supply voltage supplied by an external supply to the chipcontaining the circuit of FIG. 1 and the memory matrix 1. For example,this supply voltage may be 5 V, 3 V or 1.8 V. The node 11 has aconductive branch 13 for connecting the low-voltage stage 101 to thehigh-voltage stage 102.

[0022] The high-voltage stage 102 includes current-amplification meanscomprising, for example, a current amplifier 14 provided with an inputterminal 6 connected to the conductive branch 13, and with the outputterminal 7. In particular, this current amplifier 14 is of the invertingtype. That is, it supplies at the output terminal 7 a current having anamplitude equal to the amplitude of the current present at the inputterminal 6, multiplied by a suitable gain factor A and has a phase whichis opposite the phase of the current present at the input terminal 6.

[0023] The current amplifier 14 preferably has an input stage withsuitably low impedance so that the pole which this input stageintroduces in the transfer function of the reading circuit of FIG. 1 isa non-dominant pole disposed sufficiently out of band so as not tocritically affect the stability of the circuit with feedback.

[0024] Typically, the current amplifier 14 is supplied by a voltageV_(pp) greater than the supply voltage V_(dd). The voltage V_(pp) may beobtained from the voltage V_(dd) by positive voltage-boosters orcharge-pump circuits of conventional type and formed by integration. Theoutput node 7 of the amplifier 14 is connected to the gate terminal G ofthe memory cell 2.

[0025] This output node 7 is also connected to a compensation capacitor15 with a capacitance C_(L) which in turn is connected between the node7 and ground. Typically, this capacitor 15 has a capacitance C_(L)suitably greater than the equivalent stray capacitance due to othercomponents connected to the output node 7, such as the gate G of thecell 2, the line decoder 3, and the conductive branch 16. In selectingthe dimensions of the circuit of FIG. 1, it is thus possible to ignorethe capacitive contributions of these elements, which cannot bedetermined precisely beforehand, and to make reference to thecapacitance C_(L) of predetermined value. For example, the capacitor 15may have a capacitance of a few pF.

[0026] The capacitor 15 is such that it can be charged and discharged bythe output current of the amplifier 14 to generate the control voltageto be applied to the gate terminal G. The current amplifier 14 ispreferably such as to have an output stage having an impedance ofsuitably high value so that, together with a suitable value of thecapacitance C_(L) of the capacitor 15, the pole at the output node 7 isa dominant pole of the transfer function of the reading circuit ofFIG. 1. In this case, the feedback circuit shown in FIG. 1 has atransfer function which can be approximated to a single-pole functionand the circuit is thus unconditionally stable.

[0027] The gate terminal G is connected to the analog/digital converter5, of conventional type, which enables the analog voltage generated atthe output node 7 to be converted into a set or word of n bitscorresponding to the data stored in the memory cell 2.

[0028] The operation of the feedback circuit 100 for supplying to thegate terminal G of the memory 2 the control voltage V_(G) to cause thecurrent present at the drain terminal D of the cell to adopt apredetermined value I_(0cell) will now be described. The gate controlvoltage V_(GR) (evaluated in the steady state) for which the absorptionof the current I_(0cell) is obtained is correlated unequivocally withthe threshold voltage V_(TH) programmed in the memory cell 2 inaccordance with the equation:

V _(GR) =V _(TH) +V _(0V)  (1)

[0029] in which the voltage V_(0V) is the overdrive voltage necessaryfor the current I_(0cell) flow in the memory cell 2.

[0030] In an initial stage, the gate voltage of the memory cell 2addressed by the decoders 3 and 4 is set at an initial value V₀ which,advantageously, is selected within a range ΔV_(th) of variation of thethreshold voltages. For example, this range ΔV_(th) extends between 2Vand 6.5 V.

[0031] At the initial voltage V₀, the memory cell 2 absorbs a currentI_(cell) (which may even be zero) which is multiplied by the factor mdefined above by the current mirror 10 and is then supplied to the node11. With reference to the direction of the current flow indicated inFIG. 1, in the branch 13, there is a current I_(e) equal to thedifference between the current mI_(cell) output by the current mirror 10and the current I_(REF) generated by the current generator 12:I_(e)=mI_(cell)−I_(REF). The node 11 has the function of a comparisonnode between the current derived from the cell 2 and multiplied by thecurrent mirror 10 and the reference current I_(REF), while the currentI_(e) represents an error signal for the feedback circuit 100.

[0032] A situation in which the current mI_(cell) is less than thecurrent I_(REF) will now be considered. This corresponds to thesituation in which the current I_(cell) is less than the currentI_(0cell) defined above. In this condition, the overdrive voltage V_(OV)of the memory cell 2 is less than the value indicated by equation (1)and therefore, in order to set the current I_(0cell) in the memory cell2, it is necessary to raise the voltage V_(G) of the gate terminal G.Upon the assumption mentioned above, the current I_(e) input to thecurrent amplifier 14 has a negative sign and the amplifier 14 suppliesto the output terminal 7 a current I_(u) of a sign and amplitude such asto charge the capacitor 15, bringing the gate terminal G to a voltagevalue V_(G) greater than the initial value V₀.

[0033] It is assumed that, at this voltage value V_(G)′, the currentmI_(cell) becomes greater than the reference current I_(REF) In thiscase, an increase takes place in the current I_(e) relative to the valueadopted previously, causing the current amplifier 14 to output a currentof a sign and amplitude such as at least partially to discharge thecapacitor 15, and consequently to reduce the voltage of the gateterminal G of the memory cell 2. This control of the voltage V_(G) Ofthe gate terminal G of the memory cell 2 continues until an equilibriumcondition is reached, in which the current I_(e) input to the currentamplifier 14 is zero.

[0034] In the embodiment described, the current amplifier 14 isadvantageously supplied by a voltage V_(pp) greater than the supplyvoltage V_(dd) since the control voltage to be applied to the gateterminal G of the memory cell 2 is normally greater than the voltageV_(dd) supplied by the supply alone. The reading of the memory cell 2 iscompleted by converting the voltage V_(GR) applied to the gate terminalG of the cell into the word of n bits corresponding to the dataprogrammed in the cell by the analog/digital converter 5.

[0035] By introducing a current multiplication factor, the currentmirror 10 enables a comparison to be performed in the node 11 betweencurrents of relatively high value so as to minimize the weight of anyinaccuracies in the reference current I_(REF). This enables the readingcircuit described above to operate with high performance in terms ofaccuracy, permitting correct reading of multilevel memory cells and, inparticular, cells having more than eight possible programming levels.

[0036] Moreover, the use of the current mirror 10 limits the currentabsorbed by the cell (for example, to less than 15-20 μA) and hence thestress to which the cell is subjected, and lengthening the average lifeof the data stored. Furthermore, as stated above, the current mirror 10can be supplied by the supply voltage V_(dd) and does not thereforerequire the use of positive voltage-booster devices.

[0037] The use of the high voltages in the feedback circuit 100 isoptimized, keeping performance high in terms of accuracy. In fact, inthe reading circuit 100, only those stages for which the supply voltageV_(dd) may be insufficient, as may be the case, for example, for thestage 102 comprising the current amplifier 14, are supplied by thevoltage V_(pp) generated by one or more positive voltage-boosters. Alimited number of positive voltage-boosters can therefore be used forthe circuit of FIG. 1, or positive voltage-boosters of small dimensionsmay be used, reducing power consumption and the area occupied by thecircuit on a semiconductor chip. In particular, with the use ofmultilevel memory cells, the saving in area avoids canceling out thegain in area achieved by the multilevel technology.

[0038] Moreover, with regard to stability, the behavior of the feedbackcircuit 100 is improved in comparison with that of known readingcircuits. In fact, as sated above, the input stage of the currentamplifier 14 can have dimensions such that they do not give rise toinstability. In particular, the input stage and the output stage of thecurrent amplifier 14 may have dimensions such as to render the circuitwith feedback of FIG. 1 unconditionally stable.

[0039] The greater stability which can be achieved by the feedbackcircuit 100 avoids the use of compensation circuits which cause anincrease in reading times, and thus has the advantage of enabling thereading circuit to operate at fast speeds. On the basis of the foregoingdescription, a person skilled in the art can easily design particularcircuit configurations which implement the functions of the blocks shownin FIG. 1.

[0040] For completeness of description, some possible circuitconfigurations which may be used for these functional blocks are shownin FIG. 2. For simplicity of representation, FIG. 2 does not show theline decoder 3, the column decoder 4 or the memory matrix 1, for whichcapacitors and resistors of suitable capacitance and resistance may besubstituted.

[0041] The memory cell 2 has its drain terminal connected to a firstterminal or node 51 of the bitline limiter 8. Moreover, to take accountof the capacitive contribution of the column decoder 4, of thecapacitance of the drain terminal D of the memory cell 2, and of thecapacitances of the drain terminals of other memory cells of the columnof the matrix 1 to which the cell 2 belongs, a capacitor of capacitanceC_(BL) has been introduced, disposed between the node 51 and ground.

[0042] The bitline limiter 8, the operation of which is known to aperson skilled in the art, is advantageously supplied with low voltage,that is, with the standard supply voltage V_(dd). It is stressed thatthe bitline limiter 8 enables the capacitive weight of the firstterminal 51 connected to the drain terminal D of the memory cell 2 to beignored. In fact, the bitline limiter 8 keeps the voltage of the firstterminal 51 substantially constant by causing that terminal to appear asa ground, and hence to have a low resistance for a dynamic signal. Thismeans that the bitline limiter 8 is not significant for the stability ofthe circuit of FIG. 1.

[0043] A second terminal of the bitline limiter 8 is connected to theinput branch of the current mirror 10 which comprises, in the embodimentshown, a PMOS transistor M₂ having a drain terminal connected to its owngate terminal. The current mirror 10 also comprises a PMOS transistor M₃having a gate terminal connected to the gate terminal of the transistorM₂. The transistors M₂ and M₃ are supplied by the supply voltage V_(dd)at their source terminals.

[0044] As is clear to a person skilled in the art, during the operationof the current mirror 10, at a drain of the transistor M₃, there is acurrent equal to the current present at the drain terminal of thetransistor M₂, multiplied by the above mentioned multiplication factorm, which depends on the aspect ratios of the transistors M₂ and M₃.

[0045] The transistor M₃ of the current mirror 10 has its drain terminalconnected to the node 11 which enables the current output by the currentmirror 10 to be compared with the reference current I_(REF) supplied bythe current generator 12. This node 11 is connected to the inputterminal 6 of the current amplifier 14 which comprises an input stage 54and an output stage including a first current mirror 17 and a secondcurrent mirror 18.

[0046] The input stage 54 includes an NMOS transistor M₄ and a PMOStransistor M₅ which are biased in a common-gate arrangement and haverespective source terminals connected to the input terminal 6 in orderto receive the current I_(e). The transistor M₄ has a drain terminalconnected to the first current mirror 17, which includes two PMOStransistors, and the transistor M₅ has a drain terminal connected to thesecond current mirror 18, which includes two NMOS transistors. Moreover,the transistors M₄ and M₅ have gate terminals connected, respectively,to a biasing stage. This stage may have dimensions such that the inputstage 54 operates in Class AB.

[0047] For example, the biasing stage includes a first NMOS biasingtransistor M₁₀ having a drain terminal connected, by a resistor ofresistance R_(HV), to a terminal to which the voltage V_(pp) obtained bysuitably amplifying the supply voltage V_(dd) is supplied. The firstbiasing transistor M₁₀ has a source terminal connected to a sourceterminal of a second biasing transistor PMOS M₁₁ having a drain terminalconnected to a generator 63 of a current I_(HV) and then to ground. Thefirst and the second biasing transistors M₁₀, M₁₁ are connected asdiodes, that is, they have their respective gate terminals connected totheir drain terminals.

[0048] Moreover, the gate terminals of the two biasing transistors M₁₀and M₁₁ are connected to the gate terminals of the transistors M₄ andM₅, respectively, so as to supply a suitable biasing voltage thereto.The dimensions of the biasing stage enables the static current which theamplifier 14 will absorb in the steady state, that is, in the presenceof a zero signal, to be set by the positive voltage-boosters. The valueof this current is fixed by the current supplied by the currentgenerator I_(HV).

[0049] It is pointed out that, by causing the current amplifier 14 tooperate in class AB, the advantage is achieved, that the behavior of thereading circuit according to the invention is rendered symmetrical inthe sense that its performance during the stage of the charging of thecapacitor 15 is substantially equivalent to its performance in the stageof the discharge thereof.

[0050] The initial biasing conditions of the capacitor 15 mayadvantageously be arranged in the center of the range within which thevoltage of the gate terminal of the memory cell read will be regulated.Moreover, it will be noted that the input stage 54 including thetransistors M₄ and M₅ connected in a common-gate arrangement, has a lowinput impedance which enables the advantages set out above in terms ofstability and speed to be achieved.

[0051] The first current mirror 17 includes a PMOS transistor M₆ havinga gate terminal connected to its own drain terminal and to the drainterminal of the transistor M₄ included in the input stage 54. The gateterminal of the transistor M₆ is also connected to a gate terminal of aPMOS transistor M₈ having a drain terminal connected to the output node7.

[0052] The transistors M₆ and M₈ have respective source terminalsconnected to a terminal at which the voltage V_(pp) is available. Inoperation, this first current mirror supplies at the drain terminal ofthe transistor M₈, a current equal to the current present at the drainterminal of the transistor M₆, multiplied by a suitable multiplicationfactor M.

[0053] The second current mirror 18 includes an NMOS transistor M₇having a drain terminal connected to its own gate terminal and to thedrain terminal of the transistor M₅ of the input stage 54. Moreover, thegate terminal of the transistor M₇ is connected to a gate terminal of aNMOS transistor M₉ having a drain terminal connected to the output node7. The transistors M₇ and M₉ have respective source terminals connectedto ground. In operation, this second current mirror 18 supplies, at thedrain terminal of the transistor M₉, a current equal to the currentpresent at the drain terminal of the transistor M₇, multiplied by asuitable multiplication factor which, for the purposes of symmetry ofthe reading circuit, is preferably equal to the multiplication factor ofthe first current mirror.

[0054] It is pointed out that the output impedance of the amplifier 14,that is, the impedance seen by the output node 7, is given by theimpedance seen at the drains of the transistors M₈ and M₉, each of whichis connected in a common-source arrangement and hence is such as to havea high impedance. As stressed above, by a suitable selection of theoutput impedance of the transistors M₈ and M₉ and of the capacitanceC_(L) of the capacitor 15, it is possible to achieve a transfer functionof the reading circuit of FIG. 2 having substantially a single pole.

[0055] With reference to the operation of the amplifier 14, it ispointed out that, when the current I_(e) present in the branch 13increases relative to an equilibrium value, an increase takes place inthe current which passes through the PMOS transistor M₅ in the inputstage 54 and which enters the transistor M₇ of the second current mirror18. The second current mirror 18 will have an increasing current in thedirection into the drain terminal of the transistor Mg and such assuitably to discharge the capacitor 15 through the node 7.

[0056] When the current I_(e) present in the branch 13 decreasesrelative to an equilibrium value, an increase takes place in the currentwhich passes through the NMOS transistor M₄ in the input stage 54 andwhich leaves the drain terminal of the transistor M₆ included in thefirst current mirror 17. The first current mirror 17 will have anincreasing current in the direction out of the drain terminal of thetransistor M₈ and such as suitably to charge the capacitor 15 throughthe node 7.

[0057] The insertion of a circuit embodiment of the feedback circuit 100in a reading circuit has demonstrated the advantages offered by thepresent invention. With the reading circuit described above, it ispossible to achieve reading times considerably shorter than thoseachieved by the circuits formed in accordance with the prior art. Infact, to reach the gate-control voltage with a deviation of less than 5mV from the steady-state value, the circuit according to the inventiontook a time of less than 250 ns and, in particular, less than 120 ns.Moreover, a current absorption by the positive voltage-boosters of lessthan 20 μA during static operation, and a dynamic current absorption ofabout 200 μA for a period of about 50 ns, were observed.

[0058] High performance in terms of accuracy, stability, reading times,consumption and overall size which can be achieved by the readingcircuit according to the invention are particularly advantageous formultilevel memories. This enables the multilevel approach to be usedeven with a number of levels greater than eight, unlike conventionalreading circuits. The use of multilevel memories with large storagecapacities is particularly advantageous in the field of portable devicessuch as, for example, mobile telephones, electronic diaries, Walkmans™,cameras and digital video cameras.

That which is claimed is:
 1. A circuit for reading a non-volatile memorycell (2) having an output terminal (D) for an output current and acontrol terminal (G) for receiving a voltage for controlling the outputcurrent, the circuit comprising: a feedback circuit (100) which can beconnected electrically to the output terminal and to the controlterminal in order to generate the control voltage from a referencesignal and from the output current, characterized in that the feedbackcircuit comprises current-amplification means (14) having a firstterminal (6) for receiving a current-error signal derived from thereference signal and from the output current, and a second terminal (7)for supplying an amplified current.
 2. A reading circuit according toclaim 1, further comprising: current-generating means (12) forgenerating the reference signal, a comparison node (11) electricallyconnectible to the current-generating means and to the output terminal(D) of the memory cell (2), the comparison node being such as to supplyto the first terminal (6) of the amplification means (14) thecurrent-error signal derived from the difference between the referencesignal and a first current correlated with the output current.
 3. Areading circuit according to claim 1 in which the amplified current hasa phase opposed to the phase of the current-error signal.
 4. A readingcircuit according to claim 1 in which the current-amplification means(14) comprise an input stage (54) having input impedance of low value sothat a non-dominant pole is associated with the input stage.
 5. Areading circuit according to claim 4 in which the current-amplificationmeans (14) comprise an output stage (M₈; M₉; 15) having an impedance ofhigh value so that the transfer function of the reading circuit has adominant pole associated with the output stage.
 6. A reading circuitaccording to claim 1 in which the second terminal (7) is operativelyconnected to the control terminal (G) of the memory cell (2) and acapacitive compensation element (15) is connected to the secondterminal, and can be charged and discharged by the amplified currentsupplied by the current-amplification means (14) in order to generatethe control voltage.
 7. A reading circuit according to claim 6 in whichthe capacitive element (15) has a capacitance greater at least than astray capacitance associated with the second terminal (7).
 8. A readingcircuit according to claim 2 in which a current mirror (10) isinterposed between the comparison node (11) and the output terminal (D)in order to generate the first current from the output current.
 9. Areading circuit according to claim 8 in which the current-generatingmeans (12) and the current mirror (10) can be supplied with a firstsupply voltage and the current-amplification means (14) can be suppliedwith a second voltage greater than the first supply voltage.
 10. Areading circuit according to claim 1 in which the current-amplificationmeans (14) comprise a current amplifier in class AB.
 11. A readingcircuit according to claim 4 in which the input stage (54) comprises aninput transistor (M₄) and a second input transistor (M₅) havingrespective source terminals connected to the first terminal (6), each ofthe first and second input transistors being biased in a common-gatearrangement.
 12. A reading circuit according to claim 5 in which theoutput stage comprises a first current mirror (17) and a second currentmirror (18) which are connected to the second terminal (7) in order tomultiply a current supplied by the input stage by a multiplicationfactor and to supply the amplified current to the second terminal.
 13. Areading circuit according to claim 12 in which the first and secondcurrent mirrors (17, 18) comprise respective output transistors (M₈, M₉)which are connected to the second terminal (7), each of the first andsecond output transistors being biased with a common-source arrangement.14. A reading circuit according to claim 1 in which the amplificationmeans comprise MOSFETs.
 15. A reading circuit according to claim 1 inwhich voltage-limiting means (8) are connected to the output terminal(D) of the memory cell (2) for keeping the voltage of the outputterminal substantially constant.
 16. A reading circuit according toclaim 1 in which the control terminal (G) of the memory cell (2) isconnected to an analog-digital converter (5) for converting the controlvoltage into a digital word correlated with a threshold voltageprogrammed in the memory cell.
 17. An integrated circuit comprising: amatrix of non-volatile memory cells (1) having a plurality of memorycells arranged in rows and columns, the plurality including a memorycell (2) provided with an output terminal (D) for an output current andwith a control terminal (G) for receiving a voltage for controlling theoutput current, characterized in that the circuit comprises a readingcircuit formed in accordance with at least one of claims 1 to 16, forreading the memory cell.
 18. An integrated circuit according to claim 17in which the reading circuit comprises a line decoder (3) and a columndecoder (4) which are operatively associated with the memory matrix (1)in order to select a memory cell of the plurality on the basis of anaddress signal.
 19. An integrated circuit according to claim 17 in whichthe reading circuit is formed in accordance with claim 9, the firstsupply voltage being a supply voltage of the integrated circuit suppliedfrom outside the integrated circuit, and the second supply voltage beinggenerated within the integrated circuit, from the first supply voltage.20. An integrated circuit according to claim 17 in which the pluralityof memory cells are multilevel cells each programmable to a plurality ofprogramming levels.